module ahb_slave(clk,reset,HSEL,HADDR,HBURST,HSIZE,HTRANS,HWRITE,HWDATA,HRDATA,HREADY,HRESP,STALL_pre);
   
   parameter                  SLAVE_NUM = 0;
   
   input                      clk;
   input                      reset;
   input		      HSEL;
   
   input [31:0]               HADDR;
   input [2:0]                HBURST;
   input [1:0]                HSIZE;
   input [1:0]                HTRANS;
   input                      HWRITE;
   input [31:0]               HWDATA;
   input                      STALL_pre;
	
   output [31:0]              HRDATA;
   output                     HREADY;
   output                     HRESP;


   
   wire                       WR;
   wire                       RD;
   wire [8:0]                ADDR_WR;
   wire [8:0]                ADDR_RD;
   wire [31:0]                DIN;
   wire [31:0]                DOUT;
   

   
     ahb_slave_ram ahb_slave_ram(
               		   .clk(clk),
               		   .reset(reset),
			   .HSEL(HSEL),
                           .HADDR(HADDR[23:0]),
                           .HBURST(HBURST),
                           .HSIZE(HSIZE),
                           .HTRANS(HTRANS),
                           .HWRITE(HWRITE),
                           .HWDATA(HWDATA),
                           .HRDATA(HRDATA),
                           .HREADY(HREADY),
                           .HRESP(HRESP),
			   .STALL_pre(STALL_pre),
                           .WR(WR),
                           .RD(RD),
                           .ADDR_WR(ADDR_WR),
                           .ADDR_RD(ADDR_RD),
                           .DIN(DIN),
                           .DOUT(DOUT)
                           		);
   
   
   ahb_slave_mem ahb_slave_mem(
			  .clk(clk),
			  .reset(reset),
			  .WR(WR),
			  .RD(RD),
			  .ADDR_WR(ADDR_WR),
			  .ADDR_RD(ADDR_RD),
			  .DIN(DIN),
			  .DOUT(DOUT)
             				);


   
   
endmodule




